期刊论文

中文

中国集成电路

1681-5289

2023

32

07

41-47

10.3969/j.issn.1681-5289.2023.07.008

本校为第一机构

本文对基-2 FFT算法进行了改进，采用并行流水线结构，设计实现了一种低延时可配置的快速傅里叶变换（Fast Fourier Transform, FFT）加速器。提出了一种新型“二分法”频率抽取的方法，按FFT运算顺序抽取数据，减少了等待时间；优化每一级FFT运算存储单元数量及旋转因子存储方式，降低了存储资源需求。基于Verilog语言完成FFT加速器的设计，采用Matlab和Modelsim完成数值计算和仿真验证，仿真结果与计算结果一致。加速器支持可配置采样点数作为输入进行运算，在时钟频率为200MHz时，完成一次1024点复数FFT运算仅需2.65μs。

The FFT accelerator is improved on the basis of Radix-2 FFT algorithm by adopting the structure of a parallel pipeline,a low-delay and configurable Fast Fourier Transform(FFT)accelerator is designed in this paper.A new technique has been proposed for frequency extractio...MORE The FFT accelerator is improved on the basis of Radix-2 FFT algorithm by adopting the structure of a parallel pipeline,a low-delay and configurable Fast Fourier Transform(FFT)accelerator is designed in this paper.A new technique has been proposed for frequency extraction based on the bisection method,in which the data ar...