期刊论文

Design of Pixel Clock Recovery at Receiving End of Image Transmission Based on FPGA

中文

电子科技

1007-7820

2013

26

12

114-117

10.16180/j.cnki.issn1007-7820.2013.12.028

湖南省教育厅科研基金资助项目（11C0068）； 长沙市科技计划基金资助项目（K1101005-11）； 长沙理工大学***基金资助项目（10xxrc004）； 湖南省重点学科建设基金资助项目； 长沙理工大学精品课程基金资助项目（KC1128）；

本校为第一机构

根据Xilinx Spartan-6中PLL的结构与相关特性,提出了一种在图像传输中动态配置像素时钟的方法.在发送端,将不同的像素时钟经过编码并与图像数据一起发送至接收端,接收端接收到编码值,并通过PLL动态重配置恢复出对应的像素时钟,可以在1.4 μs完成图像传输格式的在线切换.该设计接口简单、变频速度快、实时性强、稳定性高、灵活性好,已成功应用到某光端机产品中.

According to the structure and related features of PLL in Xilinx Spartan-6, a method is proposed for configuring the pixel clock in the image transmission dynamically. The encoded value from different pixel clocks and the image data from the transmitting end are sent to the receiving end, and the corresponding pixel clock is recovered through PLL dynamic reconfiguration with on-line switchover of the image transmission formats in 1.4 μs. This de- sign features a simple interface, fast speed frequency conversion, hard real-time, high stability, instantaneity and flexibilit...